NEW APPROACH OF SIGNED BINARY NUMBERS MULTIPLICATION AND ITS IMPLEMENTATION ON FPGA

Sarifuddin Madenda; Suryadi Harmanto

doi:10.35760/tr.2021.v26i1.3703

NEW APPROACH OF SIGNED BINARY NUMBERS MULTIPLICATION AND ITS IMPLEMENTATION ON FPGA

Sarifuddin Madenda
Universitas Gunadarma
Indonesia

Suryadi Harmanto
Universitas Gunadarma
Indonesia

DOI: http://dx.doi.org/10.35760/tr.2021.v26i1.3703

Abstract

This paper proposes a new model of signed binary multiplication. This model is formulated mathematically and can handle four types of binary multipliers: signed positive numbers multiplied by signed positive numbers (SPN-by-SPN); signed positive numbers multiplied by signed negative numbers (SPN-by-SNN); signed negative numbers multiplied by signed positive numbers (SNN-by-SPN); and signed negative numbers multiplied by signed negative numbers (SNN-by-SNN). The proposed model has a low complexity algorithm, is easy to implement in software coding and integrated in a hardware FPGA (Field-Programmable Gate Array), and is more powerful compared to the modified Baugh-Wooley's model.

Keywords

Signed Binary Numbers; Signed Multiplication; Algorithm; Multiplier Circuit; FPGA

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